This disclosure relates to coherence management in a data processing system that utilizes range-based memory address system. Data processing systems, such as a System-on-a-Chip (SoC) may contain multiple processor cores, multiple data caches, and shared data resources. In a shared memory system for example, each of the processor cores may read and write to a single shared address space. Cache coherency is an issue in any system that contains one or more caches and more than one device sharing data in a single cached area. There are two potential problems with a system that contains caches. Firstly, memory may be updated (by another device) after a cached device has taken a copy. At this point, the data within the cache is out-of-date or invalid and no longer contains the most up-to-date data. Secondly, systems that contain write-back caches must deal with the case where the device writes to the local cached copy at which point the memory no longer contains the most up-to-date data. A second device reading memory will see out-of-date (stale) data.
On a current page-based memory system, when data from a virtual address range is page into a physical address range previously occupied by data belonging to another virtual address range, the new data is broadcast through the coherence network on a cache line granularity (number of cache lines per page is equal to the page granularity (e.g., 4-kilobytes)) so that every core on that coherence network is not flushed of the old data values for the physical address range in question.
When an out-of-coherence network device wishes to gain a specific coherence states over a range of address, the coherence state of any data stored in caches must be modified. For a standard page-based memory system, this problem is handled by issuing cache maintenance instructions for some or all elements within the target address range (typically at page granularity, e.g., 64 separate requests for a 4-kilobyte page). A broadcast is necessary for each of those separate requests regardless of if the data is extant in the caches or not.